1. Field of the Invention
The present invention relates to a semiconductor device, and particularly relates to a semiconductor device having a plurality of stacked semiconductor chips electrically connected to one another by penetration electrodes that penetrating through the semiconductor chips.
2. Description of Related Art
The storage capacity required for a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) is increasing in recent years. To meet this demand, there is recently proposed a memory device called “multi-chip package” in which a plurality of memory chips are stacked. However, because of the need to provide wires connecting the respective memory chips to a package substrate, it is difficult to stack many memory chips in the multi-chip package.
On the other hand, there is recently proposed a semiconductor device of such a type that a plurality of memory chips each provided with penetration electrodes are stacked. The penetration electrodes may be referred to as through silicon vias. In the semiconductor device of this type, the through silicon vias provided in each of the memory chips are connected to those provided in upper and lower memory chips. Accordingly, the number of through silicon vias connected to the package substrate does not increase even if the number of stacks increases. Therefore, it is possible to stack more memory chips (see Japanese Patent Application Laid-open Nos. 2006-313607 and 2007-158237, and International Publication No. WO2007/032184).
In the stacked semiconductor device, the through silicon vias provided at the same plane position as viewed from a stacking direction, are basically short-circuited. However, as described in Japanese Patent Application Laid-open No. 2006-313607, a part of the through silicon vias are not short-circuited and those arranged at different plane positions, as viewed from the stacking direction, are often connected to one another. Such through silicon vias are used to apply different signals to the respective semiconductor chips.
On the other hand, because many through silicon vias are provided in the semiconductor chips, a part of the through silicon vias often becomes defective and the defective through silicon vias need to be relieved by being replaced by auxiliary through silicon vias. Specifically, as described in Japanese Patent Application Laid-open No. 2007-158237, there is proposed a method of connecting a plurality of through silicon vias in parallel in advance or making regular through silicon vias replaceable by auxiliary through silicon vias. Furthermore, International Publication No. WO2007/032184 describes a method of commonly allocating an auxiliary through silicon via to a plurality of through silicon vias.
With the method of connecting the through silicon vias in parallel, if any of the through silicon vias has a non-conductive defect, it is possible to relieve the through silicon via. However, it is impossible to relieve the through silicon via if the through silicon via has a short-circuit defect (short-circuit to a power supply line or another through silicon via). Furthermore, the large increase in the number of necessary through silicon vias causes not only the increase in an occupation area of the through silicon vias on each of the chips but also the increase in the load of the through silicon vias as a result of the parallel connection of the through silicon vias. Therefore, there is a problem that it is required to improve the capability of a driver for driving these through silicon vias.
With the method of replacing the regular through silicon via by the auxiliary through silicon via, it is necessary for each through silicon via to include a switching circuit, which results in the increase in the occupation area of the through silicon vias on each chip. Particularly on a signal path on which the through silicon vias that are arranged at the different plane positions, as viewed from the stacking direction, are short-circuited, each through silicon via is used only to supply signals to one corresponding semiconductor chip and does not contribute to supplying signals to the other semiconductor chips. Therefore, it is inefficient to provide the switching circuits in all of these through silicon vias, respectively.